The present invention relates to a first-in first-out memory device (called hereinafter "FIFO memory") and, more particularly, to a FIFO memory suitable for being employed in a video signal processing field such as a plane paper copier (PPC) or a facsimile apparatus (FAX).
A FIFO memory is such that data which has been written first is read out first and is thus widely employed for a serial-processing operation on data of each line in the PPC or FAX. Since a data write operation into the FIFO memory is performed in asynchronism with a data read operation therefrom, the FIFO memory includes a write control circuit independently of a data read control circuit.
Referring to FIG. 10, the FIFO memory according to the prior art includes a memory cell array 1 having a number of words each includes a plurality of bits, the number of which is equal to the number of bits of write data DTw and also equal to the number of bits of read data DTr. The write data DTw is written into the memory cell array one word by one word under the control of a write control circuit 2 responsive to a write clock signal CKw and a write reset signal RSTw. In a data read operation, on the other hand, a read control circuit 3 accesses the memory cell array to read data therefrom one word by one word in response to a read clock signal CKr and a read reset signal RSTr.
In the FIFO memory employed in the PPC or FAX, the depth of its memory capacity, i.e. the number of words, is determined in accordance with a paper size and/or resolution. For example, a paper of A3 size is used lengthwise (i.e., 297 mm) with the resolution of 40 dpi (i.e., 40 dots/mm), the FIFO memory is required to have a memory capacity of about 5K words. On the other hand, the number of bits (i.e., the bit width) of each word is determined in accordance with scale. In case of 256 scale for example, the bit width of 8-bit is required.
Thus, the FIFO memory is requested to be changeable in the number of words and accordingly in the number of bits of each word in order to satisfy the various required performances. However, the FIFO memory shown in FIG. 10 has neither function nor circuit of changing the number of bits of each word or the number of words.